The Truesilicon's AVSBus Master Controller IP provides a high-speed digital interface for controlling external voltage regulators that support the Adaptive Voltage Scaling (AVSBus) specification. The controller integrates an AMBA APB slave interface for software configuration with an AVSBus Master interface that enables rapid voltage adjustment based on processor or system power requirements. The APB interface allows software to configure voltage commands, initiate transactions, monitor communication status, and control the operation of the AVSBus master through memory-mapped registers.
The controller incorporates an internal AVSBus protocol engine that automatically generates AVSBus frames and manages communication over the dedicated three-wire interface consisting of AVS_Clock, AVS_Data, and AVS_Sync signals. The protocol engine handles command formatting, frame transmission, response reception, and timing control, enabling reliable communication with one or more AVSBus-compliant voltage regulators. By automating the protocol handling, the controller significantly reduces software overhead and simplifies system integration.
To support reliable operation, the controller provides programmable bus timing, status monitoring, timeout detection, communication error reporting, and interrupt generation for transaction completion and fault conditions. Software can operate the controller using either polling or interrupt-driven methods, allowing flexible integration into a wide range of embedded systems.
The AVSBus Master Controller IP is designed for applications requiring fast and efficient dynamic voltage control, such as Dynamic Voltage and Frequency Scaling (DVFS). It enables processors and SoCs to dynamically adjust supply voltages based on workload, thereby improving power efficiency while maintaining system performance. The controller is well suited for server processors, networking equipment, AI accelerators, FPGA platforms, storage systems, and other high-performance embedded applications.
Figure 1 illustrates the high-level architecture of the AVSBus Master Controller IP. The APB interface provides software access to the configuration and status registers, which control the AVSBus Protocol Engine. The protocol engine generates AVSBus command frames and controls the Clock Generator and AVSBus PHY to communicate with external AVSBus-compliant voltage regulators. The Interrupt Controller collects transaction completion and error events from the internal modules and generates an interrupt to notify the host processor.
