Bootloader IP
TrueSilicon’s Bootloader IP provides chip designers and architects, an efficient way to connect different AMBA protocol based IPs to memories with reduced latency, power, and area. Compliant with AMBA4 AXI
Key Benefits
- Available in native verilog (RTL)
- Linting, Synthesis, CDC, RDC are cleaned up.
- 100% Code coverage
- Verified with an expert team using comprehensive and Regression Test Suites
- IP generation tool and programmable model
- Dynamic power saving
- 24X5 customer support
Features
- AXI4 interface for writing the address vector into the SRAM for multiple IPs
- Configurable number of IPs
- Configurable reset cycles gaps in between two IPs
- Fail safe mechanism
- Small and Efficient design
- For debugging state information provided
Deliverables
- Bootloader
- IP generator & configuration tool
- Verilog test environment with verilog testcases
- IP analysis reports
- Linting report
- Synthesis report
- IP-XACT RDL generated address map
- Simulation script
- IP Block Guide
- Quick Start Guide
