The CHI NIC Coherent is a scalable, high-performance interconnect IP designed to connect processors, accelerators, memory controllers, and peripheral subsystems in modern SoCs. The interconnect supports Crossbar topologies, allowing designers to select the architecture best suited for their performance, scalability, latency, and area requirements.The Crossbar architecture provides low-latency communication for moderate node count.
The CHI NoC supports multiple Request Nodes (RN) and Slave Nodes (SN), including RN-I, RN-D, RN-F, SN-I, and SN-F, enabling seamless integration of heterogeneous compute and memory subsystems. Configurable cache line size, internal data width, and optional snoop filter support allow the interconnect to be optimized for diverse application requirements.
Supporting both Direct Memory Transfer (DMT) and Direct Cache Transfer (DCT), the interconnect handles the complete range of CHI transactions, including Read, Write, Write CMO, Atomic, DVM, and Prefetch operations. Transactions are transported as flits through a packet-switched network, with Request, Response, Data, and Snoop channels routed independently to maximize concurrency and overall throughput.
The credit-based flow control with configurable per-port credit allocation ensures reliable packet delivery while preventing congestion. QoS-based flit prioritization enables differentiated service for latency-critical traffic, and address translation support simplifies memory system integration. Designed for complex SoC environments, the CHI NIC supports communication across multiple clock, power, and voltage domains. Simplified System Address Map (SAM) configuration reduces system integration effort, while flit-level clock gating minimizes dynamic power consumption without compromising performance.
Delivered as a fully synthesizable RTL IP optimized for power, performance, and area (PPA), the CHI NIC provides a scalable, configurable, and production-ready interconnect solution for nextgeneration multicore and heterogeneous SoC platforms.
