Clock & Reset Manager IP
TrueSilicon’s Clock & Reset Manager IP provides chip designers and architects, an efficient way to connect different IPs with reduced latency, power, and area
Key Benefits
- Available in native verilog (RTL)
- Linting, Synthesis, CDC, RDC are cleaned up.
- 100% Code coverage
- Verified with an expert team using comprehensive and Regression Test Suites
- IP generation tool and programmable model
- Dynamic power saving
- 24X5 customer support
Features
- Configurable number of IPs
- Inbuilt clock divider circuit with divide factor 2,3,4,5,6,7,8,9,10, 11,12,13,14 & 15
- Inbuilt clock shifter circuit with shift factor 25%, 50%, 75%, 20%, 40%, 60% & 80%
- Mode for bypassing the clock divider & shifter circuit
- APB interface for configuring and status check of the clock & reset manager
- Clock gating for run-time clock disabling
- Reset synchronizer for RDC
Deliverables
- Clock & Reset manager
- IP generator & configuration tool
- Verilog test environment with verilog testcases
- IP analysis reports
- Linting report
- Synthesis report
- IP-XACT RDL generated address map
- Simulation script
- IP Block Guide
- Quick Start Guide
