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Low Latency AHB/APB NIC Silicon IP

Products >> Silicon IPs >> Low Latency AHB/APB NIC Silicon IP

Low Latency AHB/APB NIC Silicon IP

TrueSilicon’s AHB/APB NIC Silicon IP provides chip designers and architects with an efficient way to connect AHB and APB bus protocol supportive devices with reduced latency, power, and area.

Key Benefits

  • Available in native Verilog (RTL)
  • Linting, Synthesis, CDC, RDC are cleaned up.
  • 100% Code coverage
  • Verified with an expert team using comprehensive and Regression Test Suites
  • Consistency of interface, installation, operation, and documentation across all our IP
  • Easy GUI based integration and configuration technique
  • 24X5 customer support
  • Unique and customizable licensing models

Features

  • The Arbiter has configurable channels that can support multiple parallel operations at the same time.
  •  AMBA AHB3Lite, AHB5, APB.
  •  Secure master & slave region based on different behavior of transactions
  •  On Security mismatch NIC can send error resp or allow transaction on slave
  • Priority based transfers handling.
  • NoC Trace data available through AMBA ATB Port for easy software debug and debug Mode & Functional Mode Configurable
  • Each port data width can be different. Apart from data, other protocol supported signals can also have different widths.
  • Early response supported.
  • Supports error detection mechanism such as timeout interrupt handling.
  • Configurable memory map for different access types of memory regions.
  •  Support Logical-Physical address conversion through NIC, Default slaves
  •  Support different phase shifted frequencies for each Master & Slaves
  • Clock gating mechanism is supported
  •  Both Little and high endianness is supported
  • Within minimum latency req or rsp can propagate through NIC
  • Per port reset is available
  • Operation Mode are available such as Placement friendly, Low Congestion, Dynamic Low Power consumption, Latency friendly

Deliverables

  • AHB NIC Matrix
  • NIC Port (AHB & APB)
  • IP generator & config tool
  • Verilog test environment with verilog test cases
  • CDC constraints file (.sdc)
  • IP analysis reports
    • Linting report
    • Synthesis report
    • CDC report
  • Simulation script
  • IP Block Guide
  • IPG Guide
Download the Product Brochure from here