NoC Crossbar Silicon IP

NoC Crossbar Silicon IP

TrueSilicon’s NoC Crossbar Silicon IP provides chip designers and architects with an efficient way to connect multiple protocol bus protocol supportive devices with reduced latency, power, and area. IP available in AXI NIC, CHI NIC or multiprotocol NoC as per architecture requirements.

Key Benefits

• Available in native verilog (RTL)
• Linting, Synthesis, CDC, RDC are cleaned up.
• 100% Code coverage
• Verified with an expert team using comprehensive and Regression Test Suites
• IP generation tool and programmable model
• Dynamic power saving
• 24X5 customer support

Features

Crossbar Features

• Any number of master and slave ports is supported
• Secure master & slave region based different behaviour of transactions
• Switch base routing for proper bandwidth division & dedicated paths
• Register slicing for asynchronous interface
• Debug trace data available
• Support for different protocols for master and slave port interface
• Interrupt generation in case of error detected
• Within minimum latency request or response can transfer through NoC
• Priority based request scheduling for high performance design
• Per port reset is available

CHI Port Features

• All types of nodes supported like RN-I, RN-D & SN-I
• Support both DMT & DCT
• Address translation support
• Flit-level clock gating

AXI Port Features

• Early response supported
• Configurable data merging and breaking both possible on transfers
• Configurable outstanding & out of order for read and write separately
• Atomic transaction, Read data chunk, Interleaving, Exclusive supports

TileLink Port Features

• Support TILELINK TL-UH and TL-UL
• Support back-to-back transfers
• Response segregations of read and write

AHB Port Features

• Back-to-back transfer supports
• Early response supported
• Enable buffering

APB Port Features

• Secure Transfer
• Non-contiguous address
• Enable buffering                 

Deliverables

• NoC Matrix Crossbar
• NoC Port (CHI/AXI/AHB/APB/Tilelink)
• IP generator & configuration tool
• Verilog test environment with verilog testcases
• CDC constraints file (.sdc)
• IP analysis reports
  • Linting report
  • Synthesis report
  • CDC report
• Simulation script
• IP Block Guide
• IPG Guide