NoC Crossbar with Cache Silicon IP

 NoC Crossbar with Cache Silicon IP

TrueSilicon's NoC Crossbar with Cache Silicon IP provides chip designers and architects with an efficient way to connect multiple protocol bus protocol supportive devices with reduced latency, power, and area. It provides hardware cache coherency with software cache maintenance, NoC Silicon IP also helps to reduce the usage of interconnecting wires and resources inside the chip.

Key Benefits

• Available in native verilog (RTL)
• Linting, Synthesis, CDC, RDC are cleaned up.
• 100% Code coverage
• Verified with an expert team using comprehensive and Regression Test Suites
• IP generation tool and programmable model
• Dynamic power saving
• 24X5 customer support

Features

Crossbar Features

• Any number of master and slave ports is supported
• Secure master & slave region based on different behaviour of transactions
• Switch base router for bandwidth distribution
• Register slicing for asynchronous interface
• Debug trace data available
• Support for different protocols for master and slave port interface.
• Configurable snoop filter support
• In addition to read, write, write CMO, atomic, DVM operation & pre-fetch also supported
• Interrupt generation in case of error detected
• Within minimum latency request or response can transfer through NoC
• Priority based request scheduling for high performance design
• Per port reset is available

CHI Port Features

• All types of nodes supported like RN-I, RN-D, RN-F, SN-I & SN-F
• Multiple RN & SN supported
• Configurable cache line
• Support both DMT & DCT
• Address translation support
• Flit level clock gating

AXI Port Features

• Early response supported
• Configurable data merging and breaking both possible on transfers
• Configurable outstanding & out of order for read and write separately
• Atomic transaction, Read data chunk, Interleaving, Exclusive supports

TileLink Port Features

• Support TILELINK TL-UH, TL-UL & TL-C
• Support back-to-back transfers
• Response segregations of read and write

AHB Port Features

• Back-to-back transfer supports
• Early response supported
• Enable buffering

APB Port Features

• Secure Transfer
• Non-contiguous address
• Enable buffering                 

Deliverables

• NoC Matrix Crossbar with cache
• NoC Port (CHI/AXI/AHB/APB/Tilelink)
• IP generator & configuration tool
• Verilog test environment with verilog testcases
• CDC constraints file (.sdc)
• IP analysis reports
  • Linting report
  • Synthesis report
  • CDC report
• Simulation script
• IP Block Guide
• IPG Guide