The Multi-Protocol Coherent Network-on-Chip is a scalable, high-performance interconnect IP designed to connect processors,accelerators, memory controllers, and peripheral subsystems in modern SoCs. Supporting both Crossbar topologies, the MPC-NIC enables designers to select the architecture that best balances latency, scalability,
and area. The Crossbar architecture provides low-latency communication for moderate node counts of heterogeneous systems.
The MPC-NIC provides seamless multi-protocol connectivity through configurable protocol adapters, enabling communication between AMBA CHI, AXI, AHB, and APB based IPs within a unified packet-based interconnect. It supports multiple Request Nodes (RN) and Slave Nodes (SN), including RN-I, RN-D, RN-F, SN-I, and SN-F, allowing flexible integration of compute, memory, and peripheral subsystems. Configurable cache line size, internal data width, and optional snoop filter support enable optimization for diverse application requirements.
The interconnect supports Direct Memory Transfer (DMT), Direct Cache Transfer (DCT), and a comprehensive set of CHI transactions including Read, Write, Write CMO, Atomic, DVM, and Prefetch operations. Transactions are transferred as flits through a packet-switched network, with independent routing of Request, Response, Data, and Snoop
channels to maximize concurrency and throughput.
To ensure reliable operation, the MPC-NIC implements credit-based flow control with configurable per-port credit allocation and QoS-based flit prioritization for latency-sensitive traffic. Address translation and simplified System Address Map (SAM) configuration further simplify system integration and software development.
Designed for complex SoC environments, the MPC-NIC supports communication across multiple clock, power, and voltage domains. Flit-level clock gating minimizes dynamic power consumption, while the fully synthesizable RTL implementation is optimized for power, performance, and area (PPA).
The Multi-Protocol Coherent Network-on-Chip provides a production- ready interconnect solution for next-generation multicore and heterogeneous SoC platforms.
